1. Field of the Invention
The present invention relates in general to a sense amplifier circuit, and more particularly, to a sense amplifier circuit having current mirror architecture for semiconductor memory devices.
2. Description of the Prior Art
Since semiconductor memory devices (for example, flash memory, DRAM and SRAM, etc) have always been one of the most important components for electronic appliances, the performance of memory devices is highly demanded and is improving uninterruptedly.
Please refer to FIG. 1, which is a circuit diagram schematically showing the structure of a prior art sense amplifier circuit 100. The sense amplifier circuit 100 comprises a first current sensing unit 110, a second current sensing unit 130, and a latch circuit 150. The first current sensing unit 110 comprises NMOS transistors 111, 113 and 115, a PMOS transistor 117, and a first non-volatile memory unit 119. The second current sensing unit 130 comprises NMOS transistors 131, 133 and 135, a PMOS transistor 137, and a second non-volatile memory unit 139. The first non-volatile memory unit 119 comprises a PMOS transistor 123 and a first non-volatile memory device 121. The second non-volatile memory unit 139 comprises a PMOS transistor 143 and a second non-volatile memory device 141. The first and second non-volatile memory devices 121 and 141 are embedded memory cells, which can be floating-gate (FG) PMOS embedded memory cells.
The first and second current sensing units 110 and 130 are both coupled between a high bias supply Vdd and a low bias supply Vss. The latch circuit 150 comprises two inverters 151 and 153 coupled in series, with the output of one inverter electrically connected back to the input of the other inverter. The latch function of the pair of cross-coupled inverters 151 and 153 is a well-known prior art and, for the sake of brevity, further discussion is omitted.
The NMOS transistors 111 and 131 are turned on or off in response to a control signal RE. The NMOS transistors 113 and 133 together with the PMOS transistors 117 and 137 are turned on or off in response to a control signal ZRE. The PMOS transistors 123 and 143 are turned on or off in response to a control signal SG. The control signal ZRE is defined to be the complement of the control signal RE.
While performing a read operation, two consecutive steps, assumed to be a first step and a second step, corresponding to different control situations are required to complete the read operation. For explanation, the first non-volatile memory device 121 is assumed to be a programmed memory device and the second non-volatile memory device 141 is assumed to be an erased memory device. During the first step, the control signals RE and SG are activated and the control signal ZRE is deactivated. The term “activated” describes one signal state that assumes a high logic level, and the term “deactivated” describes the other signal state that assumes a low logic level. Accordingly, during the first step, the PMOS transistors 123 and 143 are turned off by the control signal SG, the NMOS transistors 111 and 131 are turned on by the control signal RE, the PMOS transistors 117 and 137 are turned on by the control signal ZRE and the NMOS transistors 113 and 133 are turned off by the control signal ZRE. Based on the situation in the first step, the voltage levels at nodes N1 and N2 are both pulled down to the low voltage level Vss, and the voltage levels at nodes N3 and N4 are both pulled up to the high voltage level Vdd.
During the second step, the control signals RE and SG are deactivated and the control signal ZRE is activated. Accordingly, during the second step, the PMOS transistors 123 and 143 are turned on by the control signal SG, the NMOS transistors 111 and 131 are turned off by the control signal RE, the PMOS transistors 117 and 137 are turned off by the control signal ZRE and the NMOS transistors 113 and 133 are turned on by the control signal ZRE. Based on the situation in the second step, a first current I1 is generated through the first non-volatile memory unit 119, and a second current I2 is generated through the second non-volatile memory unit 139. Therefore, the voltage level at node N1 is boosting owing to the charge accumulation resulting from the first current I1 forwarded to the node N1, and the voltage level at node N2 is boosting owing to the charge accumulation resulting from the second current I2 forwarded to the node N2.
When the first current I1 is higher than the second current I2, the charge-accumulating rate at node N1 is also higher than that at node N2, which means that the voltage level at node N1 is boosting faster than that at node N2. Accordingly, the voltage level at node N1 is able to achieve a threshold voltage for turning on the NMOS transistor 115 precedent to that for turning on the NMOS transistor 135, which results in pulling down the voltage level at node N3 to the low voltage level Vss and the inverter 151 in turn will output a high voltage level Vdd at node N4. On the contrary, when the second current I2 is higher than the first current I1, the voltage level at node N4 is pulled down to the low voltage level Vss and the inverter 153 will output a high voltage level Vdd at node N3.
The prior art sense amplifier circuit 100 is featured by that the latch circuit 150 is latched by turning on an NMOS transistor through accumulating charge for overcoming the threshold voltage. As a result, the current difference between the first current I1 and the second current I2 is not necessary to be significant and high noise-immunity can be achieved. However, during the first step, the voltage levels at nodes N3 and N4 are both pulled up to the high voltage level Vdd. Furthermore, during the second step, the voltage levels at nodes N3 and N4 are both floated before the latch circuit 150 is latched, which means that the voltage levels at nodes N3 and N4 are both indeterminate before finishing the latch operation. That is to say, if the voltage levels at N3 and N4 are required to be always complemented to each other and be determinate before finishing the latch operation, the aforementioned prior art sense amplifier circuit cannot meet the requirements.